Embedded bridge with through-silicon vias

ABSTRACT

An apparatus comprising: a substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the package substrate, and a second conductive layer disposed between the first side and the second side of the package substrate, the substrate having dielectric material disposed between the first conductive layer and the second conductive layer; and at least one at least one bridge die disposed within the substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the second conductive layer disposed between the first and second sides of the substrate is coupled to the plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die.

BACKGROUND

In modern processor package architecture, contact pitches are shrinking to accommodate narrower and more crowded trace routing to direct increasingly faster signals within and between devices. For example, incorporation of high-bandwidth external memory with microprocessors and logic integrated circuits (ICs) in a single package requires a high-density of interconnection capability between the memory and microprocessor ICs. Conventional IC package substrate architectures typically have wide interconnect and routing pitch, and therefore do not support high-density interconnections that utilize sub-100-micron interconnect pitches. Conventional IC package substrate architectures may also require the use of bridging dies to provide an interface between low-density package substrate interconnects to high density IC interconnect architectures.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIG. 1A illustrates a cross-sectional view of a bridge die with vias interconnecting bond pads on both die surfaces, according to some embodiments of the disclosure.

FIG. 1B. illustrates a plan view of the bridge die shown in FIG. 1A, showing bond pads disposed on one die surface, according to some embodiments of the disclosure.

FIG. 1C illustrates a plan view of the bridge die shown in FIG. 1A, showing horizontally interconnected bond pads on one die surface, according to some embodiments of the disclosure.

FIGS. 2A-2I illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture illustrated in FIGS. 1A-1C, as selected operations of an exemplary fabrication method are performed, according to some embodiments of the disclosure.

FIG. 3 illustrates a cross-sectional view of a bridge die, according to some embodiments of the disclosure.

FIGS. 4A-4D illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture illustrated in FIG. 3, as selected operations of an exemplary fabrication method are performed, according to some embodiments of the disclosure.

FIG. 5 illustrates a cross-sectional view of a bridge die, according to some embodiments.

FIGS. 6A-6I illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture illustrated in FIG. 5, as selected operations of an exemplary fabrication method are performed, according to some embodiments.

FIG. 7 illustrates a cross-sectional view of a bridge die, according to some embodiments.

FIGS. 8A-8C illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture illustrated in FIG. 7, as selected operations of an exemplary fabrication method are performed, according to some embodiments.

FIG. 9A illustrates a cross-sectional view of a package substrate incorporating a bridge die with vias embedded within the package substrate, according to some embodiments of the disclosure.

FIG. 9B illustrates a plan view of the package substrate depicted in FIG. 9A, showing both low-density and high-density bond pads enabled by the embedded bridge die with TSVs, according to some embodiments of the disclosure.

FIGS. 10A-I illustrate a sequence of cross-sectional views of the build-up of package substrate with an embedded bridge die, as selected operations of an exemplary fabrication method are performed according to some embodiments.

FIG. 11 illustrates a cross-sectional view of an IC package with an embedded bridge die having through-silicon-vias (TSVs) and two external IC dies bonded to both low density and high-density bond pads on one surface of the IC package, according to some embodiments of the disclosure.

FIG. 12 illustrates a package with an embedded bridge die connecting multiple dies as part of a system-on-chip (SoC) package in an implementation of a computing device, according to some embodiments of the disclosure.

DETAILED DESCRIPTION

Interconnection between multiple chips in a single package using current package fabrication technology precludes formation of high density signal and power vias and vertical interconnects. Some embodiments combine via-mid through-silicon-via (TSV) processes and create TSVs in a bridge. As such, electrical connectivity is provided through the bridge which otherwise may limit applications of a bridge when multiple voltage rails are connected. In some embodiments, the TSVs in a bridge allows for enabling package embedded fully integrated voltage regulators (FIVRs) with and without multilayer chip inductor (MCI) in the silicon bridge. As such, more local voltage regulation options become available.

There are many technical effects of various embodiments. For example, Alternating Current (AC) noise is reduced by 24%, and peak-to-peak noise is reduced by 7% using TSV through a silicon bridge compared to wrap around power delivery solutions.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

“Bond pad” is a term referring to electrical bond pads in association with test points or external electrical connections of an integrated electronic device such as an IC or MEMS device. Related industry terms are “bond pad” and “bump”. “Solder bump” or “bump” is a ball of solder bonded to a bond pad for further assembly of the die into packages by use of surface mount technology, or for wire bonding.

Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

Views labeled “profile” and “plan” correspond to a orthogonal planes within a cartesian coordinate system. Thus, profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views.

FIG. 1A illustrates a cross-sectional view of a first embodiment of a bridge die 100 with vias interconnecting bond pads on both die surfaces, according to some embodiments.

Bridge die 100 comprises substrate 101 through which metal vias 102 extend. Bond pads 103 and 104 are disposed on both upper and lower surfaces, respectively, of substrate 101. In some embodiments, bond pads 103 are aligned with bond pads 104, and interconnected by vias 102. In some embodiments, bond pads 104 are recessed into substrate 101 and planar with the surface as shown in FIG. 1A, and in other embodiments bond pads 104 are formed directly on the surface of substrate 101. In some embodiments, substrate 101 is a silicon die. In some embodiments, substrate 101 is a silicon-on-insulator die. In some other embodiments, substrate 101 is composed of one of a float glass, borosilicate glass, silicon nitride single crystal die, etc. In some embodiments, substrate 101 is a coreless substrate.

In some embodiments, first dielectric layer 105 is disposed over one surface of substrate 101, through which vias 102 extend. In some embodiments, dielectric 105 is composed of silicon oxides. In some other embodiments, dielectric 105 is composed of one of silicon nitrides (SiN), silicon oxynitride (SiON), carbon-doped oxide (SiOC(H)), MSQ, HSQ, porous dielectrics, etc. In some embodiments, a second dielectric layer 106 is disposed over first dielectric layer 105. In some embodiments, second dielectric layer is a die backside film (DBF). In some other embodiments, second dielectric layer 106 is a B-staged epoxy film. First dielectric layers 105 is intervened between substrate 101 and bond pads 103, which are embedded in second dielectric layer 106, according to some embodiments.

FIG. 1B. illustrates a plan view of the bridge die 100 shown in FIG. 1A, showing bond pads disposed on one die surface, according to some embodiments of the disclosure.

In FIG. 1B, an exemplary configuration of bond pads 103 is shown on substrate 101, according to some embodiments. In some embodiments, bond pads 103 are aligned with bond pads 104 on the opposite side of substrate 101 (not shown in FIG. 1B), and vertically coupled with some or all of bond pads 104 by vias 102, not shown in FIG. 1B. Particular sizes and pitches of bond pads 103 vary and are dependent on the pitch requirements of the package, and the contact or solder micro-bump pitches that are built into the IC dies that are connected to bridge die 100 in packaging implementations. In some embodiments, bond pads 103 are embedded in dielectric layer 106 covering the upper surface of substrate 101.

FIG. 1C illustrates a plan view of the bridge die 100 shown in FIG. 1A, showing horizontally interconnected bond pads on one die surface, according to some embodiments of the disclosure.

In the exemplary configuration of bond pads 103 shown in FIG. 1C, some individual bond pads 103 are coupled to other bond pads 103 on the same side of substrate 101 with horizontal interconnect traces 107, 108, 109 and 110, according to some embodiments. Horizontal coupling of bond pads 103 may be desirable to couple circuits integrated on separate IC dies that are bonded to bridge die 100. Efficient signal routing and power distribution may be accomplished by architectures enabled by employment of bridge die 100. For example, coupling logic dies to Random Access Memory (RAM) dies where high-speed signal paths must be as short as possible through high-density trace routing. Power distribution may also be delivered more efficiently to IC dies coupled to bridge die 100 by routing power from package power buses directly to the IC dies, according to some embodiments.

FIGS. 2A-2I illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture 100 illustrated in FIGS. 1A-1C, as selected operations of an exemplary fabrication method are performed, according to some embodiments of the disclosure.

FIG. 2A illustrates un-revealed through-substrate vias 102 formed in substrate 101. Vias 102 are integral with bond pads 104 disposed on one surface of substrate 100, according to some embodiments. In some embodiments, substrate 101 is an entire wafer composed of a suitable material, such as silicon. In some embodiments, substrate 101 is a portion of a wafer, such as a die cut from a wafer. In FIG. 2B, substrate 101 is bonded to carrier substrate 111 by adhesive layer 112, covering bond pads 104, which are planar with the lower surface of substrate 101, according to some embodiments. In some embodiments, carrier substrate 111 is a silicon wafer or die. In some other embodiments, carrier substrate 111 can be any suitable support substrate. In some embodiments, adhesive layer 112 is disposed on a conductive layer, such as a copper foil. In some embodiments, bond pads are electrically coupled to the conductive portions of adhesive layer 112.

In FIG. 2C, the upper surface of substrate 101 is recessed to partially reveal vias 102. In some embodiments, substrate 101 is recessed by a wet etch (e.g. Potassium Hydroxide (KOH)) or in some other embodiments by reactive ion plasma etching (e.g., Deep Reactive-Ion Etching (DRIE)), which selectively removes the substrate material while vias 102 remain substantially intact. In some embodiments, the depth of the recess is not relevant to the final structure of bridge die 100. In some embodiments, the recess depth is chosen to just reveal the tips of vias 102, along with a small portion of the sidewalls near the tips, as depicted in FIG. 2C.

In FIG. 2D, first dielectric layer 105 is grown conformally over the revealed portions of vias 102 as well as the exposed surface of substrate 101. In some embodiments, first dielectric layer 105 is grown by plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, first dielectric layer is grown by RF sputtering. Other deposition techniques for growing first dielectric layer 105 include, but are not limited to, low-pressure chemical vapor deposition (LPCVD) and liquid phase deposition (LPD). In some embodiments, the thickness of first dielectric layer 105 may be chosen so that an adequate insulating layer is provided around revealed vias 102 by first dielectric layer 105, shielding the surrounding substrate (101) surface for electroplating operations in subsequent operations, according to some embodiments.

In FIG. 2E, the revealed tips of vias 102 are planarized to be level with first dielectric layer disposed on the recessed surface of substrate 101. In some embodiments, planarization may be accomplished by chemical-mechanical polishing methods. In some embodiments, tips of vias 102 are planar with first dielectric layer 105. In some embodiments, tips of vias 102 are free of dielectric material.

In FIG. 2F, bond pads 103 are formed integrally with tips of vias 102, and grow over first dielectric layer 105, such that bond pads 103 have a larger diameter than vias 102. Bond pads 103 are separated from substrate 101 by first dielectric layer 105. In some embodiments, bond pads 103 are formed by electroplating copper onto tips of vias 102, which are exposed to an electroplating bath. Vias 102 are coupled to a voltage source or potentiostat through conductive portions of adhesive layer 112 coupled to bond pads 104 on the opposite side of substrate 101, according to some embodiments. In some embodiments, bond pads 103 are formed by electro-less deposition methods. In some other embodiments, bond pads 103 are formed by vacuum deposition methods, such as sputtering or evaporation. In some embodiments, bond pads are composed of any suitable metal, and the thickness of bond pads 103 is determined by robustness of the deposited material, according to some embodiments.

In FIG. 2G, second dielectric layer 106 is deposited over first dielectric layer 105 as well as bond pads 103. In some embodiments, second dielectric layer is a laminated film, such as die backside film (DBF). In some embodiments, second dielectric layer 106 is a dry resist laminate. In some other embodiments, second dielectric layer 106 is a B-staged epoxy film that is applied by spin-coating or spray coating, then partially cured, according to some embodiments. The thickness of second dielectric layer 106 may be several 10s of microns, for example. In some embodiments, second dielectric layer 106 embeds bond pads 103.

In FIG. 2H, second dielectric layer 106 is planarized to reveal the tops of bond pads 103. The sidewalls of bond pads 103 are embedded in the remaining material of second dielectric layer 106, according to some embodiments. In some embodiments, exposed portions of bond pads 103 are substantially free of dielectric material.

In FIG. 2I, solder bumps 113 have been bonded to bond pads 103, according to some embodiments.

FIG. 3 illustrates a cross-sectional view of a second embodiment of bridge die 300, according to some embodiments of the disclosure.

In FIG. 3, a second embodiment 300 of the bridge die architecture is shown. Notably, bond pads 103 are recessed below second dielectric 106, according to some embodiments. Solder bumps 113 are partially embedded in dielectric 106, in accordance with some embodiments. In some embodiments, contacts 103 extend horizontally beyond tops of vias 102, forming on first dielectric layer 105 surrounding vias 102. In some embodiments, bond pads 103 are embedded in second dielectric 106.

FIGS. 4A-4D illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture 300 illustrated in FIG. 3, as selected operations of an exemplary fabrication method are performed, according to some embodiments of the disclosure.

In FIG. 4A, a partially complete bridge die 300 is shown bonded to carrier substrate 111. In some embodiments, the level of completion of bridge die 300 in FIG. 4A is the same as shown in FIG. 2G for bridge die 100, and description related to it and build-up in previous operations is found in the corresponding paragraphs above. In some embodiments, bond pads 103 are covered by second dielectric 106.

In FIG. 4B, openings 114 are made in second dielectric layer 106 that are aligned with bond pads 103. In some embodiments, bond pads 103 tops are exposed and substantially free of dielectric material. In some embodiments, bond pads 103 are recessed below second dielectric 106. In some embodiments, openings 114 are formed by laser skiving methods. In some embodiments, openings 114 are formed by plasma etching (e.g., DRIE). In some embodiments, second dielectric 106 is a dry photoresist, and openings 114 are formed by photolithographic methods.

In FIG. 4C, solder bumps 113 are plated into openings 114 and bonded to bond pads 103 through openings 114, according to some embodiments. In some embodiments, an epoxy flux film is applied over bumps 113. Epoxy flux films may be applied by suitable techniques (e.g., vacuum lamination at elevated temperatures to soften the epoxy film), according to some embodiments. Epoxy flux films may be implemented to enable formation of solder joints during bonding of solder bumps 113 to bond pads in the package substrate and protect the joints post-bonding.

Epoxy flux films may be planarized at lower temperatures to increase the modulus, by various methods (e.g. fly cutting), according to some embodiments. During bonding, elevated temperatures enable epoxy flux films to soften and flow over package substrate bond pads at solder reflow temperatures, facilitating high quality solder joint formation. In some embodiments, the post-bond re-solidified and cured epoxy adheres to the dielectric portions of the package substrate, increasing the bond strength of the bridge die to the package substrate beyond the strength of the solder joint bonds.

Alternatively, epoxy flux pastes (not shown) may be employed for facilitating solder joint formation, according to some embodiments. Epoxy pastes may not need lamination and planarization, and may be applied by dipping, spray coating, and spin coating, according to some embodiments. The flux pastes may be solidified by thermal curing during or after bonding, according to some embodiments.

In FIG. 4D, carrier wafer 111 and adhesion layer 112 are removed from finished bridge die 300, shown inverted from previous views. In some embodiments, implementations of bridge die 300 utilize dielectric layer 106 to help tack adhere bridge die 100 to a package substrate during build-up of the package before and during bonding of solder bumps 113 to package conductors at elevated temperatures.

FIG. 5 illustrates a cross-sectional view of a third embodiment of a bridge die 500, according to some embodiments.

In FIG. 5, a third dielectric layer 115 is added to bridge die 500 and sandwiched between first dielectric layer 105 and second dielectric layer 106. In some embodiments, third dielectric layer is composed of silicon oxides. In some other embodiments, dielectric layer 115 is composed of one of silicon nitrides (SiN), silicon oxynitride (SiON), carbon-doped oxide (SiOC(H)), Methyl silsesquioxane (MSQ), Hydrogen silsesquioxane (HSQ), porous dielectrics, etc. Other structures in and configurations in bridge die 500 are substantially the same as for bridge die 300, the description of which is provided in corresponding paragraphs above.

FIGS. 6A-6I illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture 500 illustrated in FIG. 5, as selected operations of an exemplary fabrication method are performed, according to some embodiments.

In FIG. 6A, partially complete bridge die 500 is shown at a mid-flow level. In some embodiments, bridge die 500 is at the same level of preparation as bridge die 100 shown in FIG. 2E, where vias 102 are planarized to the level of first dielectric 105.

In FIG. 6B, third dielectric layer 115 is grown over first dielectric layer 105, covering tops of vias 102, according to some embodiments. Third dielectric layer 115 may be formed by PECVD, LPCVD, sputtering techniques, and liquid phase deposition by dipping, spin and spray coating, according to some embodiments. In some embodiments, the third dielectric layer 115 is significantly thicker than first dielectric layer 105.

In FIG. 6C, openings 116 are made in third dielectric layer 115 over the tops of vias 102. In some embodiments, openings 116 are made by plasma etching (e.g., DRIE), exposing the tops of vias 102 and leaving them substantially free of dielectric.

In FIG. 6D, metallization 117 is formed in openings 116. In some embodiments, metallization 117 is formed by electroplating a suitable metal (e.g., copper) into openings 116. In some embodiments, metallization 117 is formed by electroless deposition of a metal (e.g., copper) into openings 116.

In FIG. 6E, metallization 116 and third dielectric layer are planarized, forming bond pads 103 from metallization 116. In FIG. 6F, second dielectric layer 106 is added, sandwiching third dielectric layer 115 between itself and first dielectric layer 105. In some embodiments, second dielectric layer is a die backside film laminate. In some embodiments, second dielectric layer is a dry resist laminate. In some other embodiments, second dielectric layer is a cured layer applied in the liquid state (e.g., epoxy). In some embodiments, second dielectric layer 106 covers bond pads 103.

In FIG. 6G, openings 118 are made in second dielectric layer 106 exposing tops of bond pads 102, which are recessed below second dielectric layer 106, according to some embodiments. In some embodiments, openings 118 are formed by laser skiving. In some embodiments, openings 118 are formed by plasma etching (DRIE). In some embodiments, openings 118 are formed by photolithographic methods.

In FIG. 6H, solder bumps 113 are added by plating solder in openings 118. In some embodiments, epoxy flux films or epoxy flux pastes may be coated over solder bumps 113, as described for bridge die 300.

In FIG. 6I, carrier wafer 111 and adhesion layer 112 are removed from finished bridge die 500, shown inverted from previous views, with solder bumps 113 on the lower surface of bridge die 500 in preparation for bonding with a package substrate.

FIG. 7 illustrates a cross-sectional view of a fourth embodiment 700 of a bridge die, according to some embodiments.

Bridge die 700 in FIG. 7 implements anisotropic conductive film (ACF) 119 for bonding mechanically and electrically to a package substrate layer. In some embodiments, ACF is laminated on third dielectric layer 115, and intimately covers bond pads 103, the tops of which are planar with third dielectric layer 115. In some embodiments, ACF 119 is spin coated or spray coated. ACF 119 contains conductive particles, such as carbon or gold micro- and nanoparticles, embedded in a polymeric matrix, such as a thermosetting epoxy resin. The conductivity is anisotropic in the thickness direction of the film, as conductive particles are trapped between conducting surfaces, and insulated from each other in the plane of the conducting surfaces. ACF 119 replaces solder bumps for electrical bonding.

FIGS. 8A-8C illustrate a sequence of cross-sectional views of the evolution of the bridge die architecture 700 illustrated in FIG. 7, as selected operations of an exemplary fabrication method are performed according to some embodiments.

In FIG. 8A, partially complete bridge die 700 is shown at a mid-flow level. In some embodiments, bridge die 500 is at the same level of preparation as bridge die 500 shown in FIG. 6E, where third dielectric layer 115 and metallization 117 are planarized to form exposed bond pads 103 embedded in third dielectric layer 115.

In FIG. 8B, ACF 119 is applied over third dielectric 115, covering bond pads 103. In some embodiments, ACF 119 is initially liquid and is applied by spin coating or spray coating. In some embodiments, ACF 119 is partially polymerized, and is applied by lamination. In some embodiments, ACF 119 remains partially polymerized after application.

In FIG. 8C, carrier wafer 111 and adhesion layer 112 are removed from finished bridge die 700, shown inverted from previous views, with ACF 119 on the lower surface of bridge die 700 in preparation for bonding with a package substrate.

FIG. 9A illustrates a cross-sectional view of a package substrate 900 incorporating a bridge die embedded within the package substrate, according to some embodiments of the disclosure.

Package 900 contains bridge die 901 embedded in package substrate 902. In some embodiments, lower bond pads 903 of bridge die 901 are bonded to package substrate bond pads 904 in the N−2 level conductive layer of package substrate 902. Vias 905 extend through the cross-section of bridge die 901 from lower bond pads 903 to upper bond pads 906. In some embodiments, vias 905 interconnect lower bond pads 903 and upper bond pads 906.

In some embodiments, vias 905 are through-silicon vias. In some embodiments, upper bond pads 906 of bridge die 901 are bonded to upper package substrate bond pads 907 in the N-conduction level of package substrate 902. Upper package substrate bond pads 907 are separated from one another by dielectric layer 908 disposed on top of the N-level conductive layer of package substrate 902. In some embodiments, dielectric layer 908 is a solder resist. In some embodiments, lower package substrate bond pads 904 and upper package substrate bond pads 907 are high-density bond pads.

In some embodiments, vias 909 extend vertically through package substrate 902 from the N−2 level conductive layer to the N level conductive layer, interconnecting package substrate bond pads 910 with bond pads 911. In some embodiments, package substrate bond pads 910 and 911 are low density bond pads. In some embodiments, solder bumps 912 and 913 are bonded to upper package substrate bond pads 911 and 907, respectively, for bonding to one or more IC dies.

FIG. 9B illustrates a plan view of the package substrate 900 depicted in FIG. 9A, showing both low-density and high-density bond pads enabled by the embedded bridge die with vias, according to some embodiments of the disclosure

An exemplary configuration of upper package substrate contact 907 and 911 is shown in FIG. 9B. In some embodiments, low density (e.g., large pitch) contact arrays, such as the configuration of upper package substrate bond pads 911, are interspersed with high-density (e.g., small pitch) contact arrays, represented by upper package substrate bond pads 907. Solder bumps 912 are not shown. In some embodiments, the larger bond pads of the low-density contact array, such as upper package substrate bond pads 911, handle higher currents than the high-density contact array, exemplified by the array of upper package substrate bond pads 907. In some embodiments, upper package substrate bond pads 911 deliver power to bonded IC dies.

In some embodiments, upper package substrate bond pads 907 couple to high-density signal routing on bonded IC dies. In some embodiments, bridge die vias 905 carry power. In some embodiments, power is routed through lower package substrate bond pads 904 is carried through bridge die vias 905 to upper package substrate bond pads 907 for eventual delivery to power connections on IC dies.

FIGS. 10A-10I illustrate a sequence of cross-sectional views of the build-up of package substrate 900 with embedded bridge die 901, as selected operations of an exemplary fabrication method are performed according to some embodiments.

In FIG. 10A, a partially complete package substrate 900 is shown, having been built up from level N−2 conductive layer, from which lower package substrate bond pads 904 and 910 are formed, according to some embodiments. Vias 909 extend though the dielectric 920 of package substrate 900 interconnecting lower package substrate bond pads 910 with mid-level package substrate bond pads 921. In some embodiments, mid-level package substrate bond pads 921 are formed in the N−1 level of package substrate 900.

In FIG. 10B, dielectric layer 922 is added over mid-level package substrate bond pads 921 and burying the N−1 level conductive layer. In some embodiments, dielectric 920 is ABF. In some embodiments, dielectric 921 is an epoxy resin.

In FIG. 10C, cavity 923 is formed in dielectric 920 between vias 909. In some embodiments, the bottom of cavity 923 is the N−2 level conductive layer. In some embodiments, formation of cavity 923 reveals lower package substrate bond pads 904 at the bottom of cavity 923 to be accessed in subsequent operations. In some embodiments, cavity 923 is formed by laser skiving. In some embodiments, cavity 923 is formed by plasma etching (e.g., DRIE).

In FIG. 10D, bridge die 901 is inserted in cavity 923, and bonded to lower package substrate bond pads 904 revealed at the bottom of cavity 923. In some embodiments, bonding is achieved by formation of solder joints. In some embodiments, an epoxy flux film is disposed on bridge die 901 to aid solder bonding and provide protection of the solder joints. In some embodiments, an epoxy flux paste is disposed on bridge die 901 to aid solder bonding and provide protection of the solder joints. In some embodiments, bonding is achieved by adhesion of ACF.

In FIG. 10E, an additional dielectric layer 924 is added above dielectric layer 922, covering cavity 923 and bridge die 901. In some embodiments, dielectric layer 924 is patterned with openings 925 for subsequent formation of metal structures bonded bridge die 901. In some embodiments, existing N−1 level conductive layer structures such as mid-level package substrate bond pads 921 and with upper bridge die bond pads 906 are formed in previous operations, not shown. In some embodiments, vias 926 and upper package substrate bond pads 911 are also formed by plating metal into openings formed in dielectric layers 922 and 924 during preceding operations, not shown.

In FIG. 10F, upper package substrate bond pads 907 in the N level conductive layer are formed by plating into openings 925, according to some embodiments. In FIG. 10G, solder mask resist layer 927 is laminated over upper package substrate bond pads 907 and 911, according to some embodiments. In FIG. 10H, openings 928 are formed in solder mask resist layer 927. In some embodiments, openings 928 are aligned with upper package substrate bond pads 907 and 911. In FIG. 10I, solder bumps are plated into openings 928 and bonded to bond pads N level metal structures.

FIG. 11 illustrates a cross-sectional view 1100 of package 900 with an embedded bridge die and two external IC dies bonded to both low density and high density bond pads on one surface of the IC package, according to some embodiments of the disclosure.

FIG. 11 shows package 900 with embedded bridge die 901 bonded to ICs 929 and 930. In some embodiments, ICs 929 and 930 are bonded to bridge die 901 through upper package substrate contacts 907, which accommodate the bond pad pitch of ICs 929 and 930. Power and signals are routed from lower package substrate bond pads 904 and 910 to bonded ICs 929 and 930 by intermediary of vias 905 of bridge die 901. In some embodiments, a straight-line path for power routing to ICs 929 and 930 from the bottom package level (N−2) to the top package level (N) is made possible by the package architecture exemplified by package 900. Wrap-around power routing, where power routing must be brought to ICs over the surface of the package level to which the IC are bonded, is avoided by providing an embedded bridge die having vias

In some embodiments, bridge die 901 has horizontally connected bond pads, as shown in FIG. 11 with a horizontal interconnect trace 931 connecting two upper die bond pads 907. In some embodiments, high density signal routing between separate IC dies 929 and 930 is achieved by the horizontal interconnect architecture, exemplified by the implementation of interconnect trace 931.

FIG. 12 illustrates a package with an embedded bridge die connecting multiple dies as part of a system-on-chip (SoC) package in an implementation of computing device 1200, according to some embodiments of the disclosure.

FIG. 12 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1200 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1200.

In some embodiments, computing device 1200 includes a first processor 1210. The various embodiments of the present disclosure may also comprise a network interface within 1270 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

In one embodiment, processor 1210 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1210 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1200 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

In one embodiment, computing device 1200 includes audio subsystem 1220, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1200, or connected to the computing device 1200. In one embodiment, a user interacts with the computing device 1200 by providing audio commands that are received and processed by processor 1210.

Display subsystem 1230 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1200. Display subsystem 1230 includes display interface 1232 which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1232 includes logic separate from processor 1210 to perform at least some processing related to the display. In one embodiment, display subsystem 1230 includes a touch screen (or touch pad) device that provides both output and input to a user.

I/O controller 1240 represents hardware devices and software components related to interaction with a user. I/O controller 1240 is operable to manage hardware that is part of audio subsystem 1220 and/or display subsystem 1230. Additionally, I/O controller 940 illustrates a connection point for additional devices that connect to computing device 1200 through which a user might interact with the system. For example, devices that can be attached to the computing device 1200 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

As mentioned above, I/O controller 1240 can interact with audio subsystem 1220 and/or display subsystem 1230. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1200. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1230 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1240. There can also be additional buttons or switches on the computing device 1200 to provide I/O functions managed by I/O controller 1240.

In one embodiment, I/O controller 1240 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1200. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

In one embodiment, computing device 1200 includes power management 1250 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1260 includes memory devices for storing information in computing device 1200. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1260 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1200.

Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1260) for storing the computer-executable instructions. The machine-readable medium (e.g., memory 1260) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

Connectivity via network interface 1270 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1200 to communicate with external devices. The computing device 1200 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

Network interface 1270 can include multiple different types of connectivity. To generalize, the computing device 1200 is illustrated with cellular connectivity 1272 and wireless connectivity 1274. Cellular connectivity 1272 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1274 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

Peripheral connections 1280 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1200 could both be a peripheral device (“to” 1282) to other computing devices, as well as have peripheral devices (“from” 1284) connected to it. The computing device 1200 commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1200. Additionally, a docking connector can allow computing device 1200 to connect to certain peripherals that allow the computing device 1200 to control content output, for example, to audiovisual or other systems.

In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1200 can make peripheral connections 1280 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may,” “might,” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the elements. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

Example 1 is an apparatus comprising: a substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the package substrate, and a second conductive layer disposed between the first side and the second side of the package substrate, the substrate having dielectric material disposed between the first conductive layer and the second conductive layer; and at least one at least one bridge die disposed within the substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the second conductive layer disposed between the first and second sides of the substrate is coupled to the plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die.

Example 2 includes all the features of example 1, wherein the first and second conductive layers of the substrate comprise a plurality of pads and traces.

Example 3 includes all the features of example 2, wherein the at least one bridge die comprises a plurality of pads disposed on the first side of the at least one bridge die and a plurality of pads disposed on the second side of the at least one bridge die, wherein at least a portion of the plurality of pads disposed on the first side of the at least one bridge die are interconnected by the plurality of vias to at least a portion of the plurality of pads disposed on the second side of the at least one bridge die.

Example 4 includes all the features of example 3, wherein the at least one bridge die further comprises at least one trace disposed on the first side and extending between two or more pads disposed on the first side of the at least one bridge die, wherein the two or more pads are interconnected.

Example 5 includes all the features of example 3, wherein at least a portion of the of plurality of pads disposed on the second side of the at least one bridge die is bonded to at least a portion of the plurality of pads of the second conductive layer of the substrate.

Example 6 includes all the features of example 5, wherein solder joints are disposed between the pads disposed on the second side of the at least one bridge die bonded to the pads of the second conductive layer of the substrate.

Example 7 includes all the features of example 1, wherein a dielectric layer is disposed between the second side of the at least one bridge die and the second conductive layer of the substrate.

Example 8 includes all the features of example 7, wherein the dielectric layer is a die backside film.

Example 9 includes all the features of examples 7 or 8, wherein the dielectric layer is an epoxy flux film.

Example 10 includes all the features of examples 7 or 8, wherein the dielectric layer is an epoxy flux paste.

Example 11 includes all the features of examples 7 or 8, wherein the dielectric layer is a wafer level underfill film.

Example 12 includes all the features of examples 7 to 11, wherein the dielectric film surrounds the solder joints disposed between the plurality of pads disposed on the second side of the at least one bridge die bonded to the plurality of pads disposed in the second conductive layer of the substrate.

Example 13 includes all the features of examples 7 to 12, wherein the dielectric film is bonded to a portion of the dielectric material of the substrate.

Example 14 includes all the features of example 3, wherein the die comprises an adhesive conducive film disposed over a layer of silicon oxide disposed on the second side of the at least one bridge die and forms a conductive bonding layer between the plurality of pads disposed on the second side of the at least one die and the plurality of pads disposed in the second conductive layer of the substrate.

Example 15 includes all the features of example 14, wherein the adhesive conductive film is bonded to the dielectric portions of the substrate surrounding the plurality of pads disposed in the second conductive layer of the substrate.

Example 16 includes all the features of example 1, wherein the first conductive layer of the substrate is coupled to at least a portion of the plurality of pads disposed on the first side of the at least one bridge die.

Example 17 includes all the features if examples 2 to 16, wherein at least one IC die having a first side opposed to a second side and a plurality of pads disposed on the second side of the at least one IC die aligned with and bonded to at least a portion of the plurality of pads disposed on the first side of the at least one bridge die.

Example 18 includes all the features of example 1, wherein the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to signal routing traces disposed in the second conductive layer of the substrate.

Example 19 includes all the features of examples 2 to 18, wherein the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to power routing traces disposed in the second conductive layer of the substrate.

Example 20 includes all the features of examples 2 to 19, wherein the at least one bridge die comprises voltage regulation circuitry.

Example 21 includes all the features of example 20, wherein the voltage regulation circuitry comprises one or more fully integrated voltage regulator (FIVR) integrated circuits.

Example 22 includes all the features of example 1, wherein the substrate is a coreless substrate.

Example 23 includes all the features of example 1, wherein the at least one bridge die is at least partially composed of silicon.

Example 24 includes all the features of example 23, wherein the at least one bridge die is a silicon die.

Example 25 is a system, comprising: a first active die having a first side opposing a second side, and comprising one or more logic integrated circuits formed on the first side and interconnected to a plurality of pads formed on the second side; a second active die having a first side opposing a second side, and comprising one or memory integrated circuits formed on the first side and interconnected to a plurality of pads formed on the second side; and a package substrate comprising: a first side opposing a second side, wherein a first conductive layer is disposed on the first side of the package substrate, and a second conductive layer is disposed between the first and second sides of the package substrate, and wherein the first and second conducive layers comprise a plurality of pads; and at least one at least one bridge die disposed within the package substrate and electrically coupled thereto, the at least one bridge die having a first side opposite a second side, wherein a plurality of pads is disposed on the first and second sides, and a plurality of vias interconnecting at least a portion of the plurality of pads on the first side to at least a portion of the plurality of pads on the second side of the at least one bridge die, wherein the at least one bridge die interconnects the first active die and the second active die.

Example 26 includes all the features of example 25, wherein at least a portion of the plurality of pads disposed in the second patterned conductive layer disposed between the first and second sides of the package substrate is bonded to at least a portion of the plurality of pads disposed on the second side of the at least one bridge die.

Example 27 includes all the features of example 25, wherein at least a portion of the plurality of pads disposed on the second side of the first active die and at least a portion of the plurality of pads disposed on the second side of the second active die are bonded to at least a portion of the plurality of pads disposed on the first side of the at least one bridge die.

Example 28 includes all the features of examples 25 to 27, wherein the at least one bridge die interconnects the first active die to the second active die.

Example 29 includes all the features of examples 25 to 27, wherein the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to signal routing traces disposed in the second conductive layer of the package substrate.

Example 30 includes all the features of examples 25 to 27, wherein the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to power routing traces disposed in the second conductive layer of the package substrate.

Example 31 includes all the features of examples 25 to 27, wherein the at least a portion of the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to power routing traces disposed in the second conductive layer of the package substrate and coupled to at least a portion the of plurality of pads formed on the second sides of the first active die and the second active die, wherein the at least a portion of the plurality of vias couple power from the package substrate to the first and second active dies.

Example 32 is a method, comprising: forming a package substrate having a first side and a second side, a first conductive layer disposed on the first side and a second conductive layer disposed between the first side and the second side of the substrate, a dielectric layer disposed between the first conductive layer and the second conductive layer; forming a cavity between the first conductive layer and the second conductive layer disposed between the first side and the second side of the package substrate, the second conductive layer forming the bottom of the cavity; inserting at least one bridge die into the cavity, the at least one bridge die having a first side and a second side, and a plurality of vias interconnecting at least a portion of a plurality of pads disposed on the first side to at least a portion of a plurality of pads disposed on the second side; and coupling at least a portion of the plurality of pads disposed on the second side of the at least one bridge die to the second conductive layer of the package substrate.

Example 33 includes all the features of example 32, further comprising: forming a plurality of pads in the first conductive layer of the package substrate; and coupling at least a portion of the pads formed in the first conductive layer of the package substrate to at least a portion of the plurality of pads disposed on the first side of the at least one bridge die.

Example 34 includes all the features of example 33, further comprising: depositing solder bumps onto at least a portion of the plurality of pads formed in the first conductive layer of the package substrate; and bonding at least one active die to the at least a portion of the plurality of pads formed in the first conductive layer of the package substrate.

Example 35 includes all the features of example 32, wherein coupling at least a portion of the plurality of pads disposed on the second side of the at least one bridge die to the second conductive layer of the package substrate comprises forming solder joints between the at least a portion of the plurality of pads disposed on second side of the at least one bridge die and the second conducive layer of the package substrate.

Example 36 includes all the features of example 35, wherein coupling at least a portion of the plurality of pads disposed on the second side of the at least one bridge die to the second conductive layer of the package substrate comprises forming a dielectric layer surrounding the solder joints and adhering to the dielectric portion of the package substrate.

Example 37 includes all the features of example 36, wherein forming a dielectric layer surrounding the solder joints and adhering to the dielectric portion of the package substrate comprises reflowing a die backside film disposed on the second side of the at least one bridge die.

Example 38 includes all the features of example 32, wherein coupling at least a portion of the plurality of pads disposed on the second side of the at least one bridge die to the second conductive layer of the package substrate comprises forming an adhesive conductive film bond between the at least a portion of the plurality of pads disposed on second side of the at least one bridge die and the second conducive layer of the package substrate.

Example 39 is a method, comprising: growing a plurality of vias in a substrate having a first side and a second side, the vias extending partially into the substrate from a plurality of pads disposed on the first side of the substrate; recessing the second side of the substrate to reveal the plurality of vias; growing a first dielectric layer over the second side of the substrate; planarizing the revealed plurality of vias with the first dielectric layer; forming a plurality of pads on the second side of the substrate, the pads on the second side of the substrate interconnected by the plurality of vias with the plurality of pads disposed on the first side of the substrate; depositing a second dielectric layer on the second side of the substrate, the second dielectric layer covering the plurality of pads disposed on the second side of the substrate; and forming a plurality of openings in the second dielectric layer, wherein the openings are aligned with the plurality of pads disposed on the second side of the substrate.

Example 40 includes all the features of example 39, wherein depositing a second dielectric layer on the second side of the substrate comprises depositing a die backside film on the second side of the substrate.

Example 41 includes all the features of any of examples 39 to 40, wherein depositing a second dielectric layer on the second side of the substrate comprises depositing an epoxy flux film.

Example 42 includes all the features of any of examples 39 to 40, wherein depositing a second dielectric layer on the second side of the substrate comprises depositing an epoxy flux paste.

Example 43 includes all the features of any of examples 39 to 40, wherein depositing a second dielectric layer on the second side of the substrate comprises depositing a wafer level underfill film.

Example 44 is a method, comprising: growing a plurality of vias in a substrate having a first side and a second side, the vias extending partially into the substrate from a plurality of pads disposed on the first side of the substrate; recessing the second side of the substrate to reveal the plurality of vias; growing a first dielectric layer over the second side of the substrate; planarizing the revealed plurality of vias with the first dielectric layer; growing a second dielectric layer over the planarized first dielectric layer; forming a plurality of openings in the second dielectric layer, wherein the openings are aligned with the revealed plurality of vias planar with the first dielectric layer disposed on the second side of the substrate; forming a plurality of pads in the plurality of openings in the second dielectric layer, wherein the plurality of pads is coupled to the revealed plurality of vias; planarizing the pads with the second dielectric layer; depositing a third dielectric layer over the second dielectric layer covering the plurality of pads disposed on the second side of the substrate; and forming a plurality of openings in the third dielectric layer, wherein the openings are aligned with the plurality of pads disposed on the second side of the substrate.

Example 45 includes all the features of example 44, wherein growing a second dielectric layer over the planarized first dielectric layer comprises growing any of a silicon oxide, a silicon nitride or a silicon oxynitride layer over the first dielectric layer.

Example 46 includes all the features of example 44, wherein depositing a third dielectric layer over the second dielectric layer covering the plurality of pads disposed on the second side of the substrate comprises depositing a die backside film on over the second dielectric layer.

Example 47 includes all the features of example 46, wherein depositing a die backside film on over the second dielectric layer comprises depositing any one of an epoxy flux film, an epoxy flux paste or a wafer level underfill film.

Example 48 is a method, comprising: growing a plurality of vias in a substrate having a first side and a second side, the vias extending partially into the substrate from a plurality of pads disposed on the first side of the substrate recessing the second side of the substrate to reveal the plurality of vias; growing a first dielectric layer over the second side of the substrate; planarizing the revealed plurality of vias with the first dielectric layer; growing a second dielectric layer over the planarized first dielectric layer; forming a plurality of openings in the second dielectric layer, wherein the openings are aligned with the revealed plurality of vias planar with the first dielectric layer disposed on the second side of the substrate; forming a plurality of pads in the plurality of openings in the second dielectric layer, wherein the plurality of pads is coupled to the revealed plurality of vias; planarizing the plurality of pads with the second dielectric layer; and depositing an adhesive conductive film over the second dielectric layer, wherein the adhesive conductive film contacts the plurality of pads on the second side of the substrate.

Example 49 is an apparatus, comprising: a substrate means for supporting one or more integrated circuits disposed on or in the substrate, and at least one bridge means for interconnecting the one or more integrated circuits disposed on or in the substrate, the at least one bridge means disposed within the substrate means.

Example 50 includes all the features of example 49, wherein the substrate means comprises a first conductive layer and a second conductive layer.

Example 51 includes all the features of example 50, wherein the at least one bridge means comprises vias interconnecting at least a portion of a plurality of pads disposed on a first side of the at least one bridge means with at least a portion of a plurality of pads disposed on a second side of the at least one bridge means.

Example 52 includes all the features of example 51, wherein at least a portion of the plurality of pads disposed on the second side of the at least one bridge means is coupled to the second conductive layer of the substrate means.

An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment. 

1. An apparatus, comprising: a package substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the package substrate, and a second conductive layer disposed between the first side and the second side of the package substrate, the substrate having a dielectric disposed between the first conductive layer and the second conductive layer; and at least one at least one bridge die disposed within the package substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein a first active die and a second active die are coupled to the first side of the bridge die, wherein the second conductive layer disposed between the first and second sides of the substrate is coupled to the at least plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die, wherein at least a portion of the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to power routing traces disposed in the second conductive layer of the package substrate, and wherein the at least a portion of the plurality of vias is to couple power from the package substrate to the first and second active dies.
 2. The apparatus of claim 1, wherein the first and second conductive layers comprise a plurality of pads and traces.
 3. The apparatus of claim 2, wherein the at least one bridge die comprises a plurality of pads and traces disposed on the first side of the at least one bridge die and a plurality of pads disposed on the second side of the at least one bridge die, and wherein the pads disposed on the first side of the at least one bridge die are interconnected by the plurality of vias to the pads disposed on the opposing second side of the at least one bridge die.
 4. The apparatus of claim 3, wherein the at least one bridge die comprises at least one trace disposed on the first side and extending between two or more pads disposed on the first side, and wherein the two or more pads are interconnected by the at least one trace.
 5. The apparatus of claim 3, wherein at least a portion of the plurality of pads disposed on the second side of the at least one bridge die is bonded to at least a portion of the plurality of pads of the second conductive layer of the substrate.
 6. The apparatus of claim 5, wherein solder joints are disposed between the pads disposed on the second side of the at least one bridge die bonded to the pads of the second conductive layer of the substrate.
 7. The apparatus of claim 1, wherein the dielectric is a first dielectric, and a second dielectric is disposed between the second side of the at least one bridge die and the second conductive layer of the substrate.
 8. The apparatus of claim 7, wherein the second dielectric is a die backside film.
 9. The apparatus of claim 7, wherein the second dielectric is one of an epoxy flux film, an epoxy flux paste, or a wafer level underfill film.
 10. The apparatus of claim 7, wherein the second dielectric surrounds solder joints disposed between the plurality of pads disposed on the second side of the at least one bridge die bonded to the plurality of pads disposed in the second conductive layer of the substrate.
 11. The apparatus of claim 7, wherein the second dielectric is bonded to a portion of the first dielectric.
 12. The apparatus of claim 3, wherein the die comprises an adhesive conductive film disposed over a layer of silicon oxide disposed on the second side of the at least one bridge die.
 13. The apparatus of claim 12, wherein the adhesive conductive film is bonded to the first dielectric adjacent to the plurality of pads disposed in the second conductive layer of the substrate.
 14. The apparatus of claim 1, wherein the first conductive layer of the substrate is coupled to at least a portion of the plurality of pads and traces disposed on the first side of the at least one bridge die.
 15. The apparatus of claim 2, wherein at least one active die having a first side opposed to a second side and a plurality of pads disposed on the second side are bonded to at least a portion of the plurality of pads disposed on the first side of the at least one bridge die.
 16. The apparatus of claim 1, wherein the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to signal routing traces disposed in the second conductive layer of the substrate.
 17. The apparatus of claim 2, wherein at least a portion of the traces disposed in the second conductive layer are power routing traces, wherein the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to the power routing traces disposed in the second conductive layer.
 18. The apparatus of claim 1, wherein the at least one bridge die comprises voltage regulation circuitry.
 19. The apparatus of claim 18, wherein the voltage regulation circuitry comprises one or more fully integrated voltage regulator (FIVR) integrated circuits.
 20. A system comprising: a first active die having a first side opposing a second side, and comprising one or more logic integrated circuits formed on the first side and interconnected to a plurality of pads formed on the second side; a second active die having a first side opposing a second side, and comprising one or more memory integrated circuits formed on the first side and interconnected to a plurality of pads formed on the second side; and a package substrate comprising: a first side opposing a second side, wherein a first conductive layer is disposed on the first side of the package substrate, and a second conductive layer is disposed between the first and second sides of the package substrate, and wherein the first and second conductor layers comprise a plurality of pads; and at least one at least one bridge die disposed within the package substrate and electrically coupled thereto, the at least one bridge die having a first side opposite a second side, wherein a plurality of pads is disposed on the first and second sides, and a plurality of vias interconnecting at least a portion of the plurality of pads on the first side to at least a portion of the plurality of pads on the second side of the at least one bridge die, wherein the at least a portion of the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to power routing traces disposed in the second conductor layer of the package substrate, wherein the at least a portion of the plurality of vias is to couple power from the package substrate to the first and second active dies, and wherein the at least one bridge die is to route high-speed signals between the first active die and the second active die.
 21. The system of claim 20, wherein at least a portion of the plurality of pads disposed on the second side of the first active die and at least a portion of the plurality of pads disposed on the second side of the second active die are bonded to at least a portion of the plurality of pads disposed on the first side of the at least one bridge die.
 22. The system of claim 21, wherein at least one trace is on the first side of the at least one bridge die, wherein the at least one trace interconnects two or more pads disposed on the first side of the at least one bridge die.
 23. (canceled)
 24. A method, comprising: forming a package substrate having a first side and a second side, a first conductive layer disposed on the first side and a second conductive layer disposed between the first side and the second side of the substrate, a dielectric disposed between the first conductive layer and the second conductive layer; forming a cavity between the first conductive layer and the second conductive layer disposed between the first side and the second side of the package substrate, wherein a portion of the second conductive layer is exposed and forms the bottom of the cavity; inserting at least one bridge die into the cavity, the at least one bridge die having a first side and a second side, and a plurality of vias interconnecting at least a portion of a plurality of pads disposed on the first side to at least a portion of a plurality of pads disposed on the second side; coupling at least a portion of the plurality of pads disposed on the second side of the at least one bridge die to power routing traces in the second conductive layer of the package substrate; and coupling a first active die and a second active die to the first side of the at least one bridge die, wherein the at least a portion of the plurality of vias is to couple power from the package substrate to the first and second active dies.
 25. The method of claim 24, wherein the dielectric disposed between the first conductive layer and the second conductive layer is a first dielectric, and wherein coupling at least a portion of the plurality of pads disposed on the second side of the at least one bridge die to the second conductive layer of the package substrate comprises forming solder joints between the at least a portion of the plurality of pads on the second side of the at least one bridge die and pads in the second conductive layer, and forming a second dielectric surrounding the solder joints and adhering to the first dielectric. 